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MCP79400/MCP79401/MCP79402
I2CTM Real-Time Clock/Calendar with SRAM, Unique ID and Battery Switchover
Device Selection Table
Part Number MCP79400 MCP79401 MCP79402 SRAM (Bytes) 64 64 64 Unique ID Blank EUI-48TM EUI-64TM
Description:
The MCP7940X series of low-power Real-Time Clocks (RTC) uses digital timing compensation for an accurate clock/calendar, a programmable output control for versatility, a power sense circuit that automatically switches to the backup supply, and nonvolatile memory for data storage. Using a low-cost 32.768 kHz crystal, it tracks time using several internal registers. For communication, the MCP7940X uses the I2CTM bus. The clock/calendar automatically adjusts for months with fewer than 31 days, including corrections for leap years. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator and settable alarm(s) to the second, minute, hour, day of the week, date or month. Using the programmable CLKOUT, frequencies of 32.768, 8.192 and 4.096 kHz and 1 Hz can be generated from the external crystal. Along with the battery-backed SRAM memory, a 64-bit protected EEPROM space is available for a unique ID or MAC address to be programmed at the factory or by the end user. The device is fully accessible through the serial interface while VCC is between 1.8V and 5.5V, but can operate down to 1.3V for timekeeping and SRAM retention only. The RTC series of devices are available in the standard 8-lead SOIC, TSSOP, MSOP and 2x3 TDFN packages.
Features:
* Real-Time Clock/Calendar (RTCC), Battery Backed: - Hours, Minutes, Seconds, Day of Week, Day, Month and Year - Dual alarm with single output * On-Chip Digital Trimming/Calibration: - Range -127 to +127 ppm - Resolution 1 ppm * Programmable Open-Drain Output Control: - CLKOUT with 4 selectable frequencies - Alarm output * 64 Bytes SRAM, Battery Backed * 64-Bit Unique ID: - User or factory programmable - Protected EEPROM - EUI-48TM or EUI-64TM MAC address - Custom ID programming * Automatic VCC Switchover to VBAT Backup Supply * Power-Fail Time-Stamp for Battery Switchover * Low-Power CMOS Technology: - Dynamic Current: 400 A max read - Dynamic Current: 400 A max SRAM - Battery Backup Current: <700nA @ 1.8V * 100 kHz and 400 kHz Compatibility * ESD Protection >4,000V * 1 Million Erase/Write Cycles for Unique ID * Packages include 8-Lead SOIC, TSSOP, 2x3 TDFN, MSOP * Pb-Free and RoHS Compliant * Temperature Ranges: - Industrial (I): -40C to +85C
Package Types
MSOP X1 X2 VBAT VSS 1 2 3 4 8 7 6 5 SOIC, TSSOP X1 X2 VBAT VSS 1 2 3 4 8 7 6 5 VCC MFP SCL SDA VCC MFP TDFN SCL SDA X1 1 X2 2 VBAT 3 VSS 4 8 VCC 7 MFP 6 SCL 5 SDA
2011 Microchip Technology Inc.
DS25009A-page 1
MCP7940X
FIGURE 1-1: TYPICAL OPERATING CIRCUIT
X1 Oscillator
RTCC
VCC
Time-Stamp/ Alarms
SRAM MFP
X2
VBAT
VBAT Switch
I2CTM
SCL
VSS
ID
SDA
DS25009A-page 2
2011 Microchip Technology Inc.
MCP7940X
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings ()
VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65C to +150C Ambient temperature with power applied................................................................................................-40C to +125C ESD protection on all pins 4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics: Industrial (I): VCC = +1.8V to 5.5V Min. -- 0.7 VCC -- 0.05 VCC -- -- -- -- -- -- -- -- -- -- 1.3 300 0 1.3 700 Typ. Max. -- -- 0.3 VCC 0.2 VCC -- Units -- V V V -- -- VCC = 2.5V to 5.5V (Note 1) TA = -40C to +85C Conditions
DC CHARACTERISTICS Param. No. D1 D2 D3 Sym. -- VIH VIL VHYS Characteristic SCL, SDA pins High-level input voltage Low-level input voltage Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) Low-level output voltage (MFP, SDA) Input leakage current Output leakage current Pin capacitance (SDA, SCL and MFP)
D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Note 1: 2:
VOL ILI ILO CIN, COUT
0.40 1 1 10 400 3 300 400 5 -- 1.7 -- -- 5.5
V A A pF A mA A A A nA V s s V
IOL = 3.0 ma @ VCC = 4.5V IOL = 2.1 ma @ VCC = 2.5V VIN = VSS or VCC VOUT = VSS or VCC VCC = 5.0V (Note 1) TA = 25C, f = 400 kHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V VCC = 5.5V, SCL = 400 kHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V, SCL = SDA = VCC VBAT = 1.8V @ 25C 1.5V typical at TAMB = 25C From VTRIP (max) to VTRIP (min) From VTRIP (min) to VTRIP (max) --
ICC Read Operating current ICC Write ID ICC Read Operating current ICC Write SRAM ICCS IBAT VTRIP VCCFT VCCRT VBAT Standby current (Note 2) VBAT Standby Current (Note 2) VBAT Change Over VCC Fall Time (Note 1) VCC Rise Time (Note 1) VBAT Voltage Range (Note 1)
This parameter is periodically sampled and not 100% tested. Standby with oscillator running
2011 Microchip Technology Inc.
DS25009A-page 3
MCP7940X
TABLE 1-2: AC CHARACTERISTICS
Electrical Characteristics: Industrial (I): VCC = +1.8V to 5.5V Characteristic Clock frequency Clock high time Clock low time SDA and SCL rise time (Note 1) SDA and SCL fall time (Note 1) Min. -- -- 4000 600 4700 1300 -- -- -- -- 4000 600 4700 600 0 250 100 4000 600 -- -- 4700 1300 -- -- 1M Max. 100 400 -- -- -- -- 1000 300 1000 300 -- -- -- -- -- -- -- -- -- 3500 900 -- -- 50 5 -- Units kHz ns ns ns ns ns ns ns ns ns ns ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 1.8V VCC < 2.5V 2.5V VCC 5.5V 1.8V VCC < 2.5V 2.5V VCC 5.5V 1.8V VCC < 2.5V 2.5V VCC 5.5V (Note 1 and Note 2) -- 25C, VCC = 5.5V Page mode (Note 3) TA = -40C to +85C Conditions 1.8V VCC < 2.5V 2.5V VCC 5.5V 1.8V VCC < 2.5V 2.5V VCC 5.5V 1.8V VCC < 2.5V 2.5V VCC 5.5V 1.8V VCC < 2.5V 2.5V VCC 5.5V 1.8V VCC < 2.5V 2.5V VCC 5.5V 1.8V VCC < 2.5V 2.5V VCC 5.5V 1.8V VCC < 2.5V 2.5V VCC 5.5V AC CHARACTERISTICS Param. Symbol No. 1 2 3 4 5 6 7 8 9 10 11 12 FCLK THIGH TLOW TR TF
THD:STA Start condition hold time TSU:STA Start condition setup time
THD:DAT Data input hold time TSU:DAT TSU:STO TAA TBUF Data input setup time Stop condition setup time Output valid from clock Bus free time: Time the bus must be free before a new transmission can start Input filter spike suppression (SDA and SCL pins) Write cycle time (byte or page) Endurance
13 14 15
TSP TWC --
ns ms cycles
Note 1: Not 100% tested. 2: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be obtained from Microchip's web site at www.microchip.com.
DS25009A-page 4
2011 Microchip Technology Inc.
MCP7940X
FIGURE 1-2: BUS TIMING DATA
5 2 D4 4
SCL SDA In
7 6 13
3
8
9
10
11 SDA Out
12
2011 Microchip Technology Inc.
DS25009A-page 5
MCP7940X
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
FIGURE 2-1:
DEVICE PINOUTS
SOIC/DFN/MSOP/TSSOP
X1 X2 VBAT Vss 1 2 3 4 8 7 6 5 Vcc MFP SCL SDA
2.1
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal, therefore, the SDA bus requires a pull-up resistor to VCC (typically 10 k for 100 kHz, 2 k for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.
2.2
Serial Clock (SCL)
This input is used to synchronize the data transfer from and to the device.
TABLE 2-1:
Pin Name Vss SDA SCL X1 X2 VBAT MFP Vcc
PIN DESCRIPTIONS
Pin Function Ground Bidirectional Serial Data Serial Clock Xtal Input, External Oscillator Input Xtal Output Battery Backup Input (3V Typ) Multi Function Pin +1.8V to +5.5V Power Supply
DS25009A-page 6
2011 Microchip Technology Inc.
MCP7940X
3.0
3.1
I2C BUS CHARACTERISTICS
I2C Interface
3.1.1.4
Data Valid (D)
The MCP7940X supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the Start and Stop conditions, while the MCP7940X works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. 3.1.1 BUS CHARACTERISTICS
The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device. 3.1.1.5 Acknowledge
The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 3-1). 3.1.1.1 Bus not Busy (A)
Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The MCP7940X does not generate any Acknowledge bits while an internal Unique ID programming cycle is in progress, but the user may still access the SRAM and RTCC registers.
Both data and clock lines remain high. 3.1.1.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 3.1.1.3 Stop Data Transfer (C)
A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the Acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (MCP7940X) will leave the data line high to enable the master to generate the Stop condition.
A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must end with a Stop condition.
FIGURE 3-1:
(A) SCL (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D) (D) (C) (A)
SDA
Start Condition
Address or Acknowledge Valid
Data Allowed to Change
Stop Condition
2011 Microchip Technology Inc.
DS25009A-page 7
MCP7940X
FIGURE 3-2: ACKNOWLEDGE TIMING
Acknowledge Bit
SCL
1
2
3
4
5
6
7
8
9
1
2
3
SDA
Data from transmitter
Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.
3.1.2
DEVICE ADDRESSING AND OPERATION
A control byte is the first byte received following the Start condition from the master device (Figure 3-2). The control byte consists of a control code; for the MCP7940X this is set as `1010111' for read and write operations for the Unique ID after the correct unlock sequence. The control byte for accessing the SRAM and RTCC registers are set to `1101111'. The RTCC registers and the SRAM share the same address space. The last bit of the control byte defines the operation to be performed. When set to a `1' a read operation is selected, and when set to a `0' a write operation is
selected. The next byte received defines the address of the data byte (Figure 3-3). The upper address bits are transferred first, followed by the Least Significant bits (LSb). Following the Start condition, the MCP7940X monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving an `1010111' or `1101111' code, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the MCP7940X will select a read or write operation.
FIGURE 3-3:
ADDRESS SEQUENCE BIT ASSIGNMENTS
Unique ID CONTROL BYTE ADDRESS BYTE
1
0
1
0
1
1
1 R/W
1
1
1
1
0
A 2
A 1
A 0
CONTROL CODE X = Don't Care SRAM RTCC CONTROL BYTE ADDRESS BYTE
1
1
0
1
1
1
1 R/W
X
*
*
*
*
*
*
A 0
CONTROL CODE X = Don't Care
DS25009A-page 8
2011 Microchip Technology Inc.
MCP7940X
3.1.3 ACKNOWLEDGE POLLING Since the device will not acknowledge a Unique ID command during an ID write cycle, this can be used to determine when the cycle is complete. This feature can be used to maximize bus throughput. Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK, and the master can then proceed with the next Read or Write command. See Figure 3-4 for the flow diagram.
FIGURE 3-4:
ACKNOWLEDGE POLLING FLOW
Send ID Write Command
Send Stop Condition to Initiate ID Write Cycle
Send Start
Send Control Byte with R/W = 0
Did Device Acknowledge (ACK = 0)? YES Next Operation
NO
2011 Microchip Technology Inc.
DS25009A-page 9
MCP7940X
4.0 RTCC FUNCTIONALITY
The MCP7940X family is a highly integrated RTCC. On-board time and date counters are driven from a lowpower oscillator to maintain the time and date. An integrated VCC switch enables the device to maintain the time and date and also the contents of the SRAM during a VCC power failure. * Addresses 0x00h-0x06h are the RTCC Time and Date registers. These are read/write registers. Care must be taken when writing to these registers while the oscillator is running. * Incorrect data can appear in the Time and Date registers if a write is attempted during the timeframe where these internal registers are being incremented. The user can minimize the likelihood of data corruption by insuring that any writes to the Time and Date registers occur before the contents of the second register reach a value of 0x59H. * Addresses 0x07h-0x09h are the device Configuration, Calibration and ID Unlock registers. * Addresses 0x0Ah-0x10h are the Alarm 0 registers. These are used to set up the Alarm 0, the Interrupt polarity and the Alarm 0 compare. * Addresses 0x11h-0x17h are the same as 0x0Bh0x11h but are used for Alarm 1. * Addresses 0x18h-0x1Fh are used for the timestamp feature. The Memory Map is shown in Table 4-1.
Reset State 00h 00h 00h 01h 01h 01h 01h 80h 00h 00h 00-59 00 - 59 1-12 + AM/PM 00-23 1-7 01-31 01-12 00h 00h 00h 01h 01h 01h 01h 00-59 00-59 1-12 + AM/PM 00-23 1-7 01-31 01-12 00h 00h 00h 01h 01h 01h 01h 00h 00h 00h 00h
4.1
RTCC MEMORY MAP
The RTCC registers are contained in addresses 0x00h-0x1fh. 64 bytes of user-accessable SRAM are located in the address range 0x20-0x5f. The SRAM memory is a separate block from the RTCC control and Configuration registers. All SRAM locations are battery-backed-up during a VCC power fail. Unused locations are not accessible, MCP7940X will noACK after the address byte if the address is out of range. The shaded areas are not implemented and read as `0'. No error checking is provided when loading time and date registers.
TABLE 4-1:
Address 00h 01h 02h ST Bit 7
RTCC MEMORY MAP
Bit 6 Bit 5 10 Seconds 10 Minutes 12/24 10 Hour AM/PM OSCON 10 Hour VBAT VBATEN Date Month Year ALM0 CALIBRATION UNIQUE UNLOCK ID SEQUENCE 10 Seconds 10 Minutes 12/24 10 Hour AM/PM ALM0C1 10 Hours ALM0C0 10 Month Reserved - Do not use 10 Seconds 10 Minutes 12/24 10 Hour AM/PM ALM1C1 10 Hours ALM1C0 10 Month Reserved - Do not use 10 Minutes 12/24 10 Hour AM/PM 10 Hours Minutes Hour Date Month ALM1IF Date Month Seconds Minutes Hour Day ALM0IF Date Month Seconds Minutes Hour Day EXTOSC RS2 RS1 RS0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function Seconds Minutes Hours Day Day Date Month Year Control Reg. Calibration Unlock ID Seconds Minutes Hours Day Date Month Reserved Seconds Minutes Hours Day Date Month Reserved Range 00-59 00-59 1-12 + AM/PM 00 - 23 1-7 01-31 01-12 00-99
Seconds Minutes Hour
03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh Day ALM1POL ALM1C2 ALM0POL ALM0C2 OUT SQWE
10 Date LP 10 Year ALM1 10 Month
10 Date
10 Date
10 Date 10 Month
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MCP7940X
TABLE 4-1:
Address 1Ch 1Dh 12/24 1Eh 1Fh Day Bit 7
RTCC MEMORY MAP (CONTINUED)
Bit 6 10 Minutes 10 Hour AM/PM 10 Hours Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function Range Reset State 00h 00h 00h 00h
Minutes Hour Date Month
10 Date 10 Month
4.1.1
RTCC REGISTER ADDRESSES
0x00h - Contains the BCD seconds and 10 seconds. The range is 00 to 59. Bit 7 in this register is used to start or stop the on-board crystal oscillator. Setting this bit to a `1' starts the oscillator and clearing this bit to a `0' stops the on-board oscillator. 0x01h - Contains the BCD minutes and 10 minutes. The range is 00 to 59. 0x02h - Contains the BCD hour in bits 3:0. Bits 5:4 contain either the 10 hour in BCD for 24-hour format or the AM/PM indicator and the 10-hour bit for 12-hour format. Bit 6 determines the hour format. Setting this bit to `0' enables 24-hour format, setting this bit to `1' enables 12-hour format. 0x03h - Contains the BCD day. The range is 1-7. Additional bits are also used for configuration and status. * Bit 3 is the VBATEN bit. If this bit is set, the internal circuitry is connected to the VBAT pin when VCC fails. If this bit is `0' then the VBAT pin is disconnected and the only current drain on the external battery is the VBAT pin leakage. * Bit 4 is the VBAT bit. This bit is set by hardware when the VCC fails and the VBAT is used to power the Oscillator and the RTCC registers. This bit is cleared by software. Clearing this bit will also clear all the time-stamp registers. * Bit 5 is the OSCON bit. This is set and cleared by hardware. If this bit is set, the oscillator is running, if cleared, the oscillator is not running. This bit does not indicate that the oscillator is running at the correct frequency. The RTCC will wait 32 oscillator cycles before the bit is set. The RTCC will wait roughly 32 clock cycles to clear this bit. 0x04h - Contains the BCD date and 10 date. The range is 01-31. 0x05h - Contains the BCD month. Bit 4 contains the 10 month. Bit 5 is the Leap Year bit, which is set during a leap year and is read-only. 0x06h - Contains the BCD year and 10 year. The Range is 00-99. 0x07h - Is the Control register.
* Bit 7 is the OUT bit. This sets the logic level on the MFP when not using this as a square wave output. * Bit 6 is the SQWE bit. Setting this bit enables the divided output from the crystal oscillator. * Bits 5:4 determine which alarms are active. - 00 - No Alarms are active - 01 - Alarm 0 is active - 10 - Alarm 1 is active - 11 - Both Alarms are active * Bit 3 is the EXTOSC enable bit. Setting this bit will allow an external 32.768 kHz signal to drive the RTCC registers eliminating the need for an external crystal. * Bit 2:0 sets the internal divider for the 32.768 kHz oscillator to be driven to the MFP. The duty cycle is 50%. The output is responsive to the Calibration register. The following frequencies are available: - 000 - 1 Hz - 001 - 4.096 kHz - 010 - 8.192 kHz - 011 - 32.768 kHz - 1xx enables the Cal output function. Cal output appears on MFP if SQWE is set (64 Hz Nominal). Note: The RTCC counters will continue to increment during the calibration.
0x08h is the Calibration register. This is an 8-bit register that is used to add or subtract clocks from the RTCC counter every minute. The MSB is the sign bit and indicates if the count should be added or subtracted. The remaining 7 bits, with each bit adding or subtracting 2 clocks, give the user the ability to add or subtract up to 254 clocks per minute. 0x09h is the unlock sequence address. To unlock write access to the unique ID area in the EEPROM, a sequence must be written to this address in separate commands. The process is fully detailed in Section 4.2.1 "Unlock Sequence". 0x0Ah-0x0fh and 0x11-0x16h are the Alarm 0 and Alarm 1 registers. The bits are the same as the RTCC bits with the following differences: Locations 0x10h and 0x17h are reserved and should not be used to allow for future device compatibility. 0x0Dh/0x14h has additional bits for alarm configuration.
2011 Microchip Technology Inc.
DS25009A-page 11
MCP7940X
* ALMxPOL: This bit specifies the level that the MFP will drive when the alarm is triggered. ALM2POL is a copy of ALM1POL. The default state of the MFP when used for alarms is the inverse of ALM1POL. * ALMxIF: This is the Alarm Interrupt Fag. This bit is set in hardware if the alarm was triggered. The bit is cleared in software. * ALMxC2:0: These Configuration bits determine the alarm match. The logic will trigger the alarm based on one of the following match conditions: 000 001 010 011 100 101 110 111 - - - - Seconds match Minutes match Hours match (takes into account 12/24 hour) Matches the current day, interrupt at 12.00.00 a.m. Example: 12 midnight on
4.2
4.2.1
FEATURES
UNLOCK SEQUENCE
The unique ID location is user accessible by using the unlock ID sequence. The unique ID location is 64-bits (8 bytes) and is stored in EEPROM locations 0xF0 to 0xF7. This location can be read at any time, however, a write is inhibited until unlocked. To unlock the write access to this location the following sequence must be completed: * A single write of 0x55h to address 0x09. Stop * A single write of 0xAAh to address 0x09. Stop This will allow the unique EEPROM locations to be written. After the byte or page write to these locations, the write sequence is initiated by the Stop condition. At this time, the ID locations are locked and no further writes are possible to this location unless a complete unlock sequence is repeated.
- Date - RESERVED - RESERVED - Seconds, Minutes, Hour, Day, Date, Month
* The 12/24-hour bits 0xCh.6 and 0x13h.6 are copies of the bit in 0x02h.6. The bits are read-only. 0x18h-0x1Bh are used for the timesaver function. These registers are loaded at the time when VCC fails and the RTCC operates on the VBAT. The VBAT bit is also set at this time. These registers are cleared when the VBAT bit is cleared in software. 0x1Ch-0x1Fh are used for the timesaver function. These registers are loaded at the time when VCC is restored and the RTCC switches to VDD. These registers are cleared when the VBAT bit is cleared in software. Note: It is strongly recommended that the timesaver function only be used when the oscillator is running. This will ensure accurate functionality.
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2011 Microchip Technology Inc.
MCP7940X
4.2.2 CALIBRATION
The MCP7940X utilizes digital calibration to correct for inaccuracies of the input clock source (either external or crystal). Calibration is enabled by setting the value of the Calibration register at address 08H. Calibration is achieved by adding or subtracting a number of input clock cycles per minute in order to achieve ppm level adjustments in the internal timing function of the MCP7940X. The MSB of the Calibration register is the sign bit, with a `1' indicating subtraction and a `0' indicating addition. The remaining seven bits in the register indicate the number of input clock cycles (multiplied by two) that are subtracted or added per minute to the internal timing function. The internal timing function can be monitored using the MFP open-drain output pin by setting bit [6] (SQWE) and bits [2:0] (RS2, RS1, RS0) of the control register at address 07H. Note that the MFP output waveform is disabled when the MCP7940X is running in VBAT mode. With the SQWE bit set to `1', there are two methods that can be used to observe the internal timing function of the MCP7940X: RS2 0 0 0 0 RS1 0 0 1 1 RS0 0 1 0 1 Output Signal 32768 8 4 1
With regards to the calibration function, the Calibration register setting has no impact upon the MFP output clock signal when bits RS1 and RS0 are set to `11'. The setting of the Calibration register to a non-zero value (i.e., values other than 00H or 80H) enables the calibration function which can be observed on the MFP output pin. The calibration function can be expressed in terms of the number of input clock cycles added/subtracted from the internal timing function. With bits RS1 and RS0 set to `00', the calibration function can be expressed as: Toutput where: Toutput Tinput CALREG = = = clock period of MFP output signal clock period of input signal decimal value of Calibration register setting and the sign is determined by the MSB of Calibration register. = (32768 +/- (2 * CALREG)) Tinput
A. RS2 BIT SET TO `0'
With the RS2 bit set to `0', the RS1 and RS0 bits enable the following internal timing signals to be output on the MFP pin: RS2 0 0 0 0 RS1 0 0 1 1 RS0 0 1 0 1 Output Signal 1 Hz 4.096 kHz 8.192 kHz 32.768 kHz
Since the calibration is done once per minute (i.e., when the internal minute counter is incremented), only one cycle in sixty of the MFP output waveform is affected by the calibration setting. Also note that the duty cycle of the MFP output waveform will not necessarily be at 50% when the calibration setting is applied. With bits RS1 and RS0 set to `01' or `10', the calibration function can not be expressed in terms of the input clock period. In the case where the MSB of the Calibration register is set to `0', the waveform appearing at the MFP output pin will be "delayed", once per minute, by twice the number of input clock cycles defined in the Calibration register. The MFP waveform will appear as:
The frequencies listed in the table presume an input clock source of exactly 32.768 kHz. In terms of the equivalent number of input clock cycles, the table becomes:
FIGURE 4-1:
RS1 AND RS0 WITH AND WITHOUT CALIBRATION
Delay
2011 Microchip Technology Inc.
DS25009A-page 13
MCP7940X
In the case where the MSB of the Calibration register is set to `1', the MFP output waveforms that appear when bits RS1 and RS0 are set to `01' or `10' are not as responsive to the setting of the Calibration register. For example, when outputting the 4.096 kHz waveform (RS1, RS0 set to `01'), the output waveform is generated using only eight input clock cycles. Consequently, attempting to subtract more than eight input clock cycles from this output does not have a meaningful effect on the resulting waveform. Any effect on the output will appear as a modification in both the frequency and duty cycle of the waveform appearing on the MFP output pin.
4.2.3
MFP
Pin 7 is a multi-function pin and supports the following functions: * Use of the OUT bit in the Control register for single bit I/O * Alarm Outputs - Available in VBAT mode * FOUT mode - driven from a FOSC divider - Not available in VBAT mode The internal control logic for the MFP is connected to the switched internal supply bus, this allows operation in VBAT mode. The Alarm Output is the only mode that operates in VBAT mode, other modes are suspended.
B.RS2 BIT SET TO `1'
With the RS2 bit set to `1', the following internal timing signal is output on the MFP pin: RS2 1 RS1 x RS0 x Output Signal 64.0 Hz
4.2.4
VBAT
If the VBAT feature is not being used, the VBAT pin should be connected to GND. A low-value series resistor is recommended between the external battery and the VBAT pin. The VBAT point is defined as 1.5V typical. When VDD falls below 1.5V the system will continue to operate the RTCC and SRAM using the VBAT supply. The following conditions apply:
The frequency listed in the table presumes an input clock source of exactly 32.768 kHz. In terms of the equivalent number of input clock cycles, the table becomes: RS2 1 RS1 x RS0 x Output Signal 512
TABLE 4-2:
Supply Condition VCC < VTRIP, VCC < VBAT VCC > VTRIP, VCC < VBAT VCC > VTRIP, VCC > VBAT Read/Write Access No Yes Yes Powered By VBAT VCC VCC
Unlike the method previously described, the calibration setting is continuously applied and affects every cycle of the output waveform. This results in the modulation of the frequency of the output waveform based upon the setting of the Calibration register. Using this setting, the calibration function can be expressed as: Toutput where: Toutput Tinput CALREG = = = clock period of MFP output signal clock period of input signal decimal value of the Calibration register setting, and the sign is determined by the MSB of the Calibration register. = (2 * (256 +/- (2 * CALREG))) Tinput
4.2.5
CRYSTAL SPECS
The MCP7940X has been designed to operate with a standard 32 kHz crystal. Devices with a specified load capacitance of either 12pF or 6pF can be used. The end user should fully validate the chosen crystal across all the expected design parameters of the system to ensure correct operation. The following crystals have been tested and shown to work with the MCP7940X: * CM200S 12pF surface mount crystals from Citizen * ECS-.327 12pF surface mount crystals from ECS INC * CFS206 12pF leaded crystals from Citizen This is not a definitive list and all crystals should be tested in the target application across all temperature, voltage and other significant environmental conditions.
Since the calibration is done every cycle, the frequency of the output MFP waveform is constant.
DS25009A-page 14
2011 Microchip Technology Inc.
MCP7940X
4.2.6 POWER-FAIL TIME-STAMP
The MCP7940X family of RTCC devices feature a power-fail time-stamp feature. This feature will save the time at which VCC crosses the VTRIP voltage. To use this feature, a VBAT supply must be present and the oscillator must also be running. There are two separate sets of registers that are used to record this information: * The first set located at 0x18h through 0x1Bh are loaded at the time when VCC fails and the RTCC operates on the VBAT. The VBAT (register 0x03h bit 4) bit is also set at this time. * The second set of registers, located at 0x1Ch through 0x1Fh, are loaded at the time when VCC is restored and the RTCC switches to VCC. The power-fail time-stamp registers are cleared when the VBAT bit is cleared in software.
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DS25009A-page 15
MCP7940X
5.0 ON BOARD MEMORY
The MCP7940X has both on-board Unique ID memory and battery-backed SRAM. The SRAM is arranged as 64 x 8 bytes and is retained when the VCC supply is removed, provided the VBAT supply is present and enabled. The Unique ID is nonvolatile memory and does not require the VBAT supply for retention.
5.1
SRAM
SRAM/RTCC BYTE WRITE
BUS ACTIVITY MASTER S T A R T S T O P P A C K A C K
FIGURE 5-1:
CONTROL BYTE x A C K
ADDRESS BYTE
DATA
SDA LINE BUS ACTIVITY
S1101111 0
FIGURE 5-2:
SRAM/RTCC MULTIPLE BYTE WRITE
S T A R T CONTROL BYTE x A C K A C K A C K A C K ADDRESS BYTE S T O P P
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY
DATA BYTE 0
DATA BYTE N
S11011110
The 64 bytes of user SRAM are at location 0x20h and can be accessed during an RTCC update. Upon POR the SRAM will be in an undefined state. Writing to the SRAM and RTCC is accomplished in a similar way to writing to the EEPROM (as described later in this document) with the following considerations: * There is no page. The entire 64 bytes of SRAM or 32 bytes of RTCC register can be written in one command. * The SRAM allows an unlimited number of read/ write cycles with no cell wear out. * The RTCC and SRAM are not accessible when the device is running on the external VBAT. * The RTCC and SRAM are separate blocks. The SRAM array may be accessed during an RTCC update. * Read and write access is limited to either the RTCC register block or the SRAM array. The Address Pointer will rollover to the start of the addressed block. * Data written to the RTCC and SRAM are on a per byte basis.
Note:
Entering an address past 5F for an SRAM operation will result in the MCP7940X not acknowledging the address.
DS25009A-page 16
2011 Microchip Technology Inc.
MCP7940X
5.2
5.2.1
ID
ID BYTE WRITE
Following the Start condition from the master, the control code and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the Address Pointer of the MCP7940X. After receiving another Acknowledge signal from the MCP7940X, the master device transmits the data word to be written into the addressed memory location. The MCP7940X acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and, during this time, the MCP7940X does not generate Acknowledge signals for Unique ID Write commands. If an attempt is made to write to an address and the protection is set then the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new command. After a Byte Write command, the internal address counter will point to the address location following the one that was just written.
Note:
Addressing undefined ID locations will result in the MCP7940X not acknowledging the address.
2011 Microchip Technology Inc.
DS25009A-page 17
MCP7940X
FIGURE 5-3: ID BYTE WRITE
BUS ACTIVITY MASTER S T A R T S T O P P A C K A C K CONTROL BYTE ADDRESS BYTE 11110 * * * A C K
DATA
SDA LINE BUS ACTIVITY
S1010111 0
5.2.2
READ OPERATION
Read operations are initiated in the same way as write operations with the exception that the R/W bit of the control byte is set to one. There are three basic types of read operations: current address read, random read, and sequential read. The SRAM array can be read in the same way as the ID using the control byte for the SRAM `1101111' with a valid address. 5.2.2.1 Current Address Read
the control byte again but with the R/W bit set to a one. The MCP7940X will then issue an Acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer but it does generate a Stop condition which causes the MCP7940X to discontinue transmission (Figure 5-6). After a random read command, the internal address counter will point to the address location following the one that was just read. 5.2.2.3 Sequential Read
The MCP7940X contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to one, the MCP7940X issues an Acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the MCP7940X discontinues transmission (Figure 5-5).
FIGURE 5-4:
S T A R T
CURRENT ADDRESS READ (ID SHOWN)
CONTROL BYTE DATA BYTE 11110* * * A C K N O A C K S T O P P
Sequential reads are initiated in the same way as a random read except that after the MCP7940X transmits the first data byte, the master issues an Acknowledge as opposed to the Stop condition used in a random read. This Acknowledge directs the MCP7940X to transmit the next sequentially addressed 8-bit word (Figure 5-7). Following the final byte transmitted to the master, the master will NOT generate an Acknowledge but will generate a Stop condition. To provide sequential reads, the MCP7940X contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over to the start of the Block.
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY
S 10 10111 1
5.2.2.2
Random Read
Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the MCP7940X as part of a write operation (R/W bit set to `0'). After the word address is sent, the master generates a Start condition following the Acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then, the master issues
DS25009A-page 18
2011 Microchip Technology Inc.
MCP7940X
FIGURE 5-5: RANDOM READ (UNIQUE ID SHOWN)
S T A R T CONTROL BYTE ADDRESS BYTE S T A R T CONTROL BYTE
1
BUS ACTIVITY MASTER
DATA BYTE
S T O P P
SDA LINE BUS ACTIVITY
S1 0 1 0 1 1 1 0 A C K A C K
S1 0 1 0
A C K
N O A C K
FIGURE 5-6:
BUS ACTIVITY MASTER SDA LINE
SEQUENTIAL READ (UNIQUE ID SHOWN)
CONTROL BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X S T O P P A C K A C K A C K A C K N O A C K
BUS ACTIVITY
5.3
Unique ID
The MCP7940X features an additional 64-bit unique ID area. The unique ID is located at addresses 0xF0 through 0xF7. Reading the unique ID requires the user to simply address these bytes. The unique ID area is protected to prevent unintended writes to these locations. The unlock sequence is detailed in 4.2.1 "Unlock Sequence". The unique ID can be factory programmed on some devices to provide a unique IEEE EUI-48 or EUI-64 value. In addition, customer-provided codes can also be programmed.
2011 Microchip Technology Inc.
DS25009A-page 19
MCP7940X
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
8-Lead SOIC (3.90 mm) Example:
XXXXXT XXYYWW NNN
79400I SN e3 1109 13F
8-Lead TSSOP
Example:
XXXX TYWW NNN
8-Lead MSOP Example:
9400 I109 13F
XXXXX YWWNNN
79401I 10913F
8-Lead 2x3 TDFN XXX YWW NN
Example: AAS 109 13
1st Line Marking Codes Part Number TSSOP MCP79400 MCP79401 MCP79402 Note: 9400 9401 9402 MSOP 79400T 79401T 79402T TDFN AAS AAT AAU
T = Temperature grade NN = Alphanumeric traceability code
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
DS25009A-page 20
2011 Microchip Technology Inc.
MCP7940X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
2011 Microchip Technology Inc.
DS25009A-page 21
MCP7940X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS25009A-page 22
2011 Microchip Technology Inc.
MCP7940X
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2011 Microchip Technology Inc.
DS25009A-page 23
MCP7940X
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DS25009A-page 24
2011 Microchip Technology Inc.
MCP7940X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
2011 Microchip Technology Inc.
DS25009A-page 25
MCP7940X
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DS25009A-page 26
2011 Microchip Technology Inc.
MCP7940X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
2011 Microchip Technology Inc.
DS25009A-page 27
MCP7940X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS25009A-page 28
2011 Microchip Technology Inc.
MCP7940X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
2011 Microchip Technology Inc.
DS25009A-page 29
MCP7940X
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2011 Microchip Technology Inc.
MCP7940X
APPENDIX A: REVISION HISTORY
Revision A (04/2011)
Original release of this document.
2011 Microchip Technology Inc.
DS25009A-page 31
MCP7940X
NOTES:
DS25009A-page 32
2011 Microchip Technology Inc.
MCP79400/MCP79401/MCP79402
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions.
2011 Microchip Technology Inc.
DS25009A-page 33
MCP79400/MCP79401/MCP79402
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: MCP7940X Questions: 1. What are the best features of this document? Y N Literature Number: DS25009A FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS25009A-page 34
2011 Microchip Technology Inc.
MCP7940X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not every possible ordering combination is listed below.
PART NO. Device
X
/XX
Examples: a) b) MCP79400-I/SN: Industrial Temperature, SOIC package. MCP79400T-I/SN: Industrial Temperature, SOIC package, Tape and Reel. MCP79400T-I/MNY: Industrial Temperature, TDFN package. MCP79401-I/SN: Industrial Temperature, SOIC package, EUI-48TM. MCP79401-I/MS: Industrial Temperature MSOP package, EUI-48TM. MCP79402-I/SN: Industrial Temperature, SOIC package, EUI-64TM.
MCP79402-I/ST: Industrial Temperature, TSSOP package, EUI-64TM. MCP79402-I/ST: Industrial Temperature, TSSOP package, Tape and Reel, EUI-64TM.
Temperature Package Range
MCP79400 = MCP79400T = MCP79401 = MCP79401T = MCP79402 = MCP79402T = 1.8V - 5.5V I2CTM Serial RTCC 1.8V - 5.5V I2C Serial RTCC (Tape and Ree) 1.8V - 5.5V I2C Serial RTCC, EUI-48TM 1.8V - 5.5V I2C Serial RTCC, EUI-48TM (Tape and Reel) 1.8V - 5.5V I2C Serial RTCC, EUI-64TM 1.8V - 5.5V I2C Serial RTCC, EUI-64TM (Tape and Reel)
Device:
c) d) e) f)
g)
Temperature Range: Package:
I
=
-40C to +85C
h)
SN ST
= =
MS = MNY(1) =
8-Lead Plastic Small Outline (3.90 mm body) 8-Lead Plastic Thin Shrink Small Outline (4.4 mm) 8-Lead Plastic Micro Small Outline 8-Lead Plastic Dual Flat, No Lead
Note 1: 'Y' indicates a Nickel Palladium Gold (NiPdAu) finish.
2011 Microchip Technology Inc.
DS25009A-page 35
MCP7940X
NOTES:
DS25009A-page 36
2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
ISBN: 978-1-61341-087-5
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
2011 Microchip Technology Inc.
DS25009A-page 37
Worldwide Sales and Service
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
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Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
02/18/11
DS25009A-page 38
2011 Microchip Technology Inc.

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